{"title":"基于ofdm的29.1Mbps 0.22nJ/bit主体信道通信基带收发器","authors":"Ping-Yuan Tsai, Yuyuan Chang, S. Hsu, Chen-Yi Lee","doi":"10.1109/VLSI-DAT.2015.7114538","DOIUrl":null,"url":null,"abstract":"This paper proposes an energy-efficient transceiver for body channel communication. 16-QAM OFDM is adopted to enhance the data rate and (2,1,6) convolutional code is integrated to remain the transmission reliability, where the hard-decision Viterbi Decoder gives the coding gain by 2dB. The modulator of the transceiver provides two modes - high speed mode and low power mode. In the low power mode an uneven multi-level LINC architecture is adopted. The average-power based auto gain control is applied in the receiver to ensure the transmission quality under different paste distances and different users. The chip is implemented under 90nm CMOS technology with 5.2 mm2 chip area. The data rate achieves 29.1Mbps with 6.349 mW power dissipation, resulting in 0.22nJ/b bit per energy.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"An OFDM-based 29.1Mbps 0.22nJ/bit body channel communication baseband transceiver\",\"authors\":\"Ping-Yuan Tsai, Yuyuan Chang, S. Hsu, Chen-Yi Lee\",\"doi\":\"10.1109/VLSI-DAT.2015.7114538\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes an energy-efficient transceiver for body channel communication. 16-QAM OFDM is adopted to enhance the data rate and (2,1,6) convolutional code is integrated to remain the transmission reliability, where the hard-decision Viterbi Decoder gives the coding gain by 2dB. The modulator of the transceiver provides two modes - high speed mode and low power mode. In the low power mode an uneven multi-level LINC architecture is adopted. The average-power based auto gain control is applied in the receiver to ensure the transmission quality under different paste distances and different users. The chip is implemented under 90nm CMOS technology with 5.2 mm2 chip area. The data rate achieves 29.1Mbps with 6.349 mW power dissipation, resulting in 0.22nJ/b bit per energy.\",\"PeriodicalId\":369130,\"journal\":{\"name\":\"VLSI Design, Automation and Test(VLSI-DAT)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-04-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"VLSI Design, Automation and Test(VLSI-DAT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSI-DAT.2015.7114538\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"VLSI Design, Automation and Test(VLSI-DAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI-DAT.2015.7114538","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An OFDM-based 29.1Mbps 0.22nJ/bit body channel communication baseband transceiver
This paper proposes an energy-efficient transceiver for body channel communication. 16-QAM OFDM is adopted to enhance the data rate and (2,1,6) convolutional code is integrated to remain the transmission reliability, where the hard-decision Viterbi Decoder gives the coding gain by 2dB. The modulator of the transceiver provides two modes - high speed mode and low power mode. In the low power mode an uneven multi-level LINC architecture is adopted. The average-power based auto gain control is applied in the receiver to ensure the transmission quality under different paste distances and different users. The chip is implemented under 90nm CMOS technology with 5.2 mm2 chip area. The data rate achieves 29.1Mbps with 6.349 mW power dissipation, resulting in 0.22nJ/b bit per energy.