{"title":"设计了一种新型自适应有源环路滤波电路的2ghz紧凑型锁相环","authors":"M. Toyama, S. Dosho, N. Yanagisawa","doi":"10.1109/VLSIC.2003.1221198","DOIUrl":null,"url":null,"abstract":"This paper describes a design of a compact active loop filter for Phase-Locked-Loop (PLL) with adaptive biasing technique. Using the new loop filter, the PLL can automatically adjust the loop bandwidth and damping factor to the frequency of the reference clock. Moreover, the new LPF can decrease the capacitance value to 1/10-1/20 of conventional one. A test chip was fabricated in 0.15 /spl mu/m-CMOS process. The total chip area of the PLL is reduced to 1/2 of previous one. The jitter performance is almost equal to conventionally biased PLL.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"19","resultStr":"{\"title\":\"A design of a compact 2 GHz-PLL with a new adaptive active loop filter circuit\",\"authors\":\"M. Toyama, S. Dosho, N. Yanagisawa\",\"doi\":\"10.1109/VLSIC.2003.1221198\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes a design of a compact active loop filter for Phase-Locked-Loop (PLL) with adaptive biasing technique. Using the new loop filter, the PLL can automatically adjust the loop bandwidth and damping factor to the frequency of the reference clock. Moreover, the new LPF can decrease the capacitance value to 1/10-1/20 of conventional one. A test chip was fabricated in 0.15 /spl mu/m-CMOS process. The total chip area of the PLL is reduced to 1/2 of previous one. The jitter performance is almost equal to conventionally biased PLL.\",\"PeriodicalId\":270304,\"journal\":{\"name\":\"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)\",\"volume\":\"36 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-06-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"19\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2003.1221198\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2003.1221198","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A design of a compact 2 GHz-PLL with a new adaptive active loop filter circuit
This paper describes a design of a compact active loop filter for Phase-Locked-Loop (PLL) with adaptive biasing technique. Using the new loop filter, the PLL can automatically adjust the loop bandwidth and damping factor to the frequency of the reference clock. Moreover, the new LPF can decrease the capacitance value to 1/10-1/20 of conventional one. A test chip was fabricated in 0.15 /spl mu/m-CMOS process. The total chip area of the PLL is reduced to 1/2 of previous one. The jitter performance is almost equal to conventionally biased PLL.
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