Gbps背板连接器特性的问题和挑战

C. Schuster, Y. Kwark, R. Frech, E. Klink, J. Diepenbrock, G. R. Edlund, T. Gneiting, R. Modinger
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引用次数: 3

摘要

目前的高端处理器间链路通过一个或两个连接器和几十英寸的背板以每秒千兆的数据速率运行数百个信号。合适的连接器必须满足严格的串扰、反射和衰减规范。准确的连接器测量和模型对于整个链路的成功设计至关重要。然而,由于高引脚数和与背板环境的相互依赖性,连接器的表征仍然是一项具有挑战性的任务。本文详细分析了ERNI公司的50欧姆单端粘贴式引脚原型连接器系统。进行了全面的三维全波电磁模拟,并与测量结果进行了比较。提出了几种从测试环境中提取连接器响应的去嵌入技术。将显示背板上的连接器占用面积对整体电气性能有重大影响。
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Issues and challenges of Gbps backplane connector characterization
Current high-end inter-processor links run hundreds of signals at Gigabit per second data rates over one or two connectors and tens of inches of backplane. Suitable connectors have to fulfil tight crosstalk, reflection, and attenuation specifications. Accurate connector measurements and models are critical to the successful design of the whole link. However, due to high pin count and interdependencies with the backplane environment connector characterization is still a challenging task. Here, a 50 Ohm single-ended, pin-in-paste prototype connector system from ERNI is analyzed in detail. Comprehensive 3D full-wave EM simulations were done and compared to measurements. Several de-embedding techniques are presented to extract the connector response from the test environment. It will be shown that the connector footprint on the backplane has a major impact on the overall electrical performance.
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