{"title":"C4 PowerPC微处理器芯片的CBGA封装设计:衬底可达性与性能之间的权衡","authors":"W. Huang, J. Casto","doi":"10.1109/ECTC.1994.367646","DOIUrl":null,"url":null,"abstract":"Electrical performance and printed circuit board routability tradeoff are studied in ceramic ball grid array packages (CBGAs). CBGA package design is described for a high speed chip with peripheral drivers. Three general types of array patterns are compared. First, the best routability design, where all the power and ground balls on the CBGA are routed in the center area. Second, a design with four pairs of P/G balls moved to the corners of the CBGA is evaluated, resulting in improvement of electrical performance by 50%, as measured by SSN reduction. The reasons for this improvement are analyzed. Third, even more P/G balls are moved closer to the onchip drivers, achieving an additional 30% reduction in SSN. In each case, the implications on board routability and simultaneous switching noise are assessed.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"CBGA package design for C4 PowerPC microprocessor chips: trade-off between substrate routability and performance\",\"authors\":\"W. Huang, J. Casto\",\"doi\":\"10.1109/ECTC.1994.367646\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Electrical performance and printed circuit board routability tradeoff are studied in ceramic ball grid array packages (CBGAs). CBGA package design is described for a high speed chip with peripheral drivers. Three general types of array patterns are compared. First, the best routability design, where all the power and ground balls on the CBGA are routed in the center area. Second, a design with four pairs of P/G balls moved to the corners of the CBGA is evaluated, resulting in improvement of electrical performance by 50%, as measured by SSN reduction. The reasons for this improvement are analyzed. Third, even more P/G balls are moved closer to the onchip drivers, achieving an additional 30% reduction in SSN. In each case, the implications on board routability and simultaneous switching noise are assessed.<<ETX>>\",\"PeriodicalId\":344532,\"journal\":{\"name\":\"1994 Proceedings. 44th Electronic Components and Technology Conference\",\"volume\":\"17 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-05-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1994 Proceedings. 44th Electronic Components and Technology Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ECTC.1994.367646\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1994 Proceedings. 44th Electronic Components and Technology Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECTC.1994.367646","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
CBGA package design for C4 PowerPC microprocessor chips: trade-off between substrate routability and performance
Electrical performance and printed circuit board routability tradeoff are studied in ceramic ball grid array packages (CBGAs). CBGA package design is described for a high speed chip with peripheral drivers. Three general types of array patterns are compared. First, the best routability design, where all the power and ground balls on the CBGA are routed in the center area. Second, a design with four pairs of P/G balls moved to the corners of the CBGA is evaluated, resulting in improvement of electrical performance by 50%, as measured by SSN reduction. The reasons for this improvement are analyzed. Third, even more P/G balls are moved closer to the onchip drivers, achieving an additional 30% reduction in SSN. In each case, the implications on board routability and simultaneous switching noise are assessed.<>