Reconfigurable VLSI design of processing kernel for multiple-radix single-path delay feedback FFT systems

FFT is a crucial and necessary design entity lor any current communication applications, especially for OFDM systems. As compared with conventional design approach, which can support only one-radix processing kernel of single-path delay feedback (SDF) FFT, we propose a reconfigurable processing kernel design for multiple-radix types of SDF FFT. In implementation, this kernel hardware engine is reconfigurable to deal with different computing stages and radix-types, such as 3-stage radix-2, 2-stage radix-3, and 1-stage radix-5 SDF FFT systems. Under TSMC 90nm CMOS technology, the kernel design with input/output wordlength of 16 bits only occupies 0.3068 mm2, saving 33.99% of area with respect to the summation of 3 individual single modes. Also, it only provides 13% hardware overhead as compared to pure radix-5 only processing kernel.