A differential type CMOS phase frequency detector

We propose a new differential-type CMOS phase frequency detector for a PLL design. The circuit uses two D-FFs and two delay buffers. Besides, it adopts two reset functions R1 and R2 to avoid the UP and DN being logic-1 simultaneously. Thus, any mismatch current of the charge pump circuit will not affect the performance of the PLL. The detector can greatly reduce the dead-zone phenomenon in the phase characteristic, which is important in low-jitter applications. In order to detect the smallest phase error the new detector employs delay buffers to shift the phase error. The circuit is simulated by HSPICE with the 0.35 /spl mu/m CMOS technology.