Dhirendra Kumar, Himanshu Kesarwani, Kavindra Kandpal, P. K. Misra, M. Goswami
{"title":"基于mux -亚稳态方法的高效真随机数发生器设计","authors":"Dhirendra Kumar, Himanshu Kesarwani, Kavindra Kandpal, P. K. Misra, M. Goswami","doi":"10.1109/SPIN52536.2021.9566149","DOIUrl":null,"url":null,"abstract":"The design of a meta-stable ring oscillator-based true random number generator (TRNG) is presented in this paper. The proposed circuit is designed in 40nm CMOS technology and simulated in cadence virtuoso simulation environment using a combination of current starved-based ring oscillators (ROs), multiplexer, linear feedback shift register (LFSR), UP/DOWN counter followed by a meta-stable circuit. The current starved inverter-based RO is used in place of the power-hungry comparator to save a significant amount of power dissipation observed in the existing design. The metastable circuit is used for providing randomness in the design. The proposed design had resulted in the generation of approximately 40Mbps speed, the power dissipation of 730μW, and energy efficiency of 18.25pJ/bit when designed at 1.1V. The design is fully validated by NIST 800.22 statistical test suite. The proposed design is thus highly suitable for random number generation.","PeriodicalId":343177,"journal":{"name":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design of Energy Efficient True Random Number Generator using MUX-Metastable Approach\",\"authors\":\"Dhirendra Kumar, Himanshu Kesarwani, Kavindra Kandpal, P. K. Misra, M. Goswami\",\"doi\":\"10.1109/SPIN52536.2021.9566149\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The design of a meta-stable ring oscillator-based true random number generator (TRNG) is presented in this paper. The proposed circuit is designed in 40nm CMOS technology and simulated in cadence virtuoso simulation environment using a combination of current starved-based ring oscillators (ROs), multiplexer, linear feedback shift register (LFSR), UP/DOWN counter followed by a meta-stable circuit. The current starved inverter-based RO is used in place of the power-hungry comparator to save a significant amount of power dissipation observed in the existing design. The metastable circuit is used for providing randomness in the design. The proposed design had resulted in the generation of approximately 40Mbps speed, the power dissipation of 730μW, and energy efficiency of 18.25pJ/bit when designed at 1.1V. The design is fully validated by NIST 800.22 statistical test suite. The proposed design is thus highly suitable for random number generation.\",\"PeriodicalId\":343177,\"journal\":{\"name\":\"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)\",\"volume\":\"108 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-08-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SPIN52536.2021.9566149\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SPIN52536.2021.9566149","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of Energy Efficient True Random Number Generator using MUX-Metastable Approach
The design of a meta-stable ring oscillator-based true random number generator (TRNG) is presented in this paper. The proposed circuit is designed in 40nm CMOS technology and simulated in cadence virtuoso simulation environment using a combination of current starved-based ring oscillators (ROs), multiplexer, linear feedback shift register (LFSR), UP/DOWN counter followed by a meta-stable circuit. The current starved inverter-based RO is used in place of the power-hungry comparator to save a significant amount of power dissipation observed in the existing design. The metastable circuit is used for providing randomness in the design. The proposed design had resulted in the generation of approximately 40Mbps speed, the power dissipation of 730μW, and energy efficiency of 18.25pJ/bit when designed at 1.1V. The design is fully validated by NIST 800.22 statistical test suite. The proposed design is thus highly suitable for random number generation.