迁移率调制技术对 90 纳米以下 SOI MOSFET 器件性能和可靠性的影响

W. Yeh, Chieh-Ming Lai, C. Lin, Y. Fang, H.-H. Hu, K. Chen, G. Huang
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引用次数: 0

摘要

对于 nMOSFET,利用高拉伸应力栅极盖层(GC 层)和扩散长度(LOD)来控制沟道区域的拉伸和压缩应力的方法得到了开发。在这项工作中,为了研究 GC 层薄膜厚度、LOD 和栅极宽度对器件特性和热载流子可靠性的交互应力效应,制作了具有不同 GC 层(1100A、700A、SiN380)、LOD(0.45μm∼4.5μm)和宽度(0.18μm∼10μm)的器件。结果发现,具有 700A GC 层(适当的拉伸应力)、4.5μm LOD(低压缩应力)和 0.18μm 栅极宽度(窄宽度)的器件具有更好的性能。
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The impact of mobility modulation technology on device performance and reliability for sub-90nm SOI MOSFETs
For nMOSFET, utilizing the high tensile stress gate capping layer (GC layer) and length of diffusion (LOD) to control the tensile and compressive stress in channel regions were developed. In this work, in order to investigate the interactive stress effects of GC layer film thickness, LOD and gate width on device's characteristic and hot-carrier reliability; devices with various GC layer (1100A, 700A, SiN380), LOD (0.45μm∼4.5μm) and width (0.18μm∼10μm) were fabricated. It is found that devices with 700A GC layer layer (appropriate tensile stress), 4.5μm LOD (low compressive stress) and 0.18μm gate width (narrow width) possess the better performance.
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