{"title":"用于高性能嵌入式dram的简单1晶体管无电容存储单元","authors":"P. Fazan, S. Okhonin, M. Nagoga, J. Sallese","doi":"10.1109/CICC.2002.1012775","DOIUrl":null,"url":null,"abstract":"A new compact memory architecture is proposed for embedded dynamic random access memory (eDRAM) cells. By exploiting the floating body effect of partially depleted silicon on insulator (SOI) devices, a one-transistor memory cell can be integrated in a pure logic SOI technology without adding any process step. The data retention, device operation principles and reliability make it ideal for high performance eDRAM applications while reducing the cell area by a factor of two.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"125 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"23","resultStr":"{\"title\":\"A simple 1-transistor capacitor-less memory cell for high performance embedded DRAMs\",\"authors\":\"P. Fazan, S. Okhonin, M. Nagoga, J. Sallese\",\"doi\":\"10.1109/CICC.2002.1012775\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new compact memory architecture is proposed for embedded dynamic random access memory (eDRAM) cells. By exploiting the floating body effect of partially depleted silicon on insulator (SOI) devices, a one-transistor memory cell can be integrated in a pure logic SOI technology without adding any process step. The data retention, device operation principles and reliability make it ideal for high performance eDRAM applications while reducing the cell area by a factor of two.\",\"PeriodicalId\":209025,\"journal\":{\"name\":\"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)\",\"volume\":\"125 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"23\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2002.1012775\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2002.1012775","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A simple 1-transistor capacitor-less memory cell for high performance embedded DRAMs
A new compact memory architecture is proposed for embedded dynamic random access memory (eDRAM) cells. By exploiting the floating body effect of partially depleted silicon on insulator (SOI) devices, a one-transistor memory cell can be integrated in a pure logic SOI technology without adding any process step. The data retention, device operation principles and reliability make it ideal for high performance eDRAM applications while reducing the cell area by a factor of two.
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