一种改进分水岭算法的高效体系结构及其FPGA实现

2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings. Pub Date : 2002-12-16 DOI:10.1109/FPT.2002.1188713

C. Rambabu, L. Chakrabarti, Anil Mahanta

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引用次数: 3

摘要

本文提出了一种基于Meyer模拟洪水算法的快速分水岭算法。条件邻域比较采用并行处理，一次处理3/spl次/3个像素，与Meyer算法相比，计算复杂度降低。该算法已在Xilinx FPGA环境中实现。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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An efficient architecture for an improved watershed algorithm and its FPGA implementation

This paper proposes a fast watershed algorithm derived from Meyer's simulated flooding based algorithm. The parallel processing adopted in conditional neighborhood comparisons for processing 3/spl times/3 pixels in one process leads to reduced computational complexity compared to Meyer's algorithm. The proposed algorithm has been implemented in an Xilinx FPGA environment.

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2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.

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