A 100 PS bipolar logic

AN ULTRA HIGH-SPEED bipolar integrated circuit has been developed with a propagation delay time of less than 100 ps. The process technologies involved are Elevated Electrode IC, an advanced version of SET’. The integrated transistor structure is shown in Figure 1. Arsenic doped polycrystalline silicon is used for the diffusion source as well as the elevated electrodes, emitter and collector, and also interconnection between devices. The polycrystalline silicon is processed to form an overhanging edge. In the subsequent metal evaporation process, the shadowed area under the overhanging edge functions to separate the polycrystalline silicon from the lower level, consequently the evaporated metals are isolated from another by the overhanging edge and the formation of all electrodes and interconnections is completed without the use of fine photolithography and etching processes. After the evaporation of metal on the entire surface of the circuit, the unnecessary portions are etched out by the conventional process, without precise mask alignment. The second metalization step can be made in the conventional way.