8T1R: A novel low-power high-speed RRAM-based non-volatile SRAM design

With continuous and aggressive technology scaling, suppressing the stand-by power is among the top priorities for SRAM design. Switching off the less-frequently accessed blocks is an efficient way to reduce the stand-by power, provided that the information stored in these blocks can be restored. Non-volatile memories (NVMs) are integrated into SRAM cells to perform the required store and restore functions. Among various types of NVMs, memristors (a.k.a. RRAM) have several advantages including their small device size, low voltage operation, high speed, and CMOS-compatible fabrication process. In this article, we propose a new 8T1R RRAM-based non-volatile SRAM (NV-SRAM) which adds non-volatility to the SRAM with minimum impact on the Write and Read operations. Simulation at cell-level and array-level have confirmed that the new design performs Read and Write operations at a compatible delay, energy and noise margin as the conventional 6T SRAM, and it is among the best of all reported RRAM-based NV-SRAM designs to our knowledge. In addition, since our 8T1R design uses only one RRAM device per cell, the energy required for storing/restoring the SRAM data to/from the RRAM is significantly reduced by 60%/70% compared to the lowest storing/restoring energy of the previously proposed RRAM-based NV-SRAM designs.