Energy consumption in reconfigurable mpsoc architecture: Two-level caches optimization oriented approach

In order to meet the ever-increasing computing requirement in embedded market, multiprocessor chips were proposed as the best way out. In this work we investigate the estimation of the energy consumption in embedded MPSoC system. One of the efficient solutions to reduce the energy consumption is to reconfigure the caches memories. This approach was applied for one cache level/one processor architecture. The main contribution of this paper is to explore two level data cache (L1/L2) multiprocessor architecture by estimating the energy consumption. Using a simulation platform (Multi2Simj, we first built a multiprocessor architecture, and then we propose a new modified CPACT algorithm that tunes the two-level caches memory hierarchy (L1 & L2). The caches tuning approach is based on three parameters: cache size, line size, and associativity. In this approach, and in order to find the best cache configuration, the software application is divided into several intervals and we generate automatically the best cache configuration for each interval of the application. Finally, the approach is validated using a set of open source benchmarks, Spec2006, Splash-2 and MediaBench and we discuss the performance in terms of speedup and energy reduction.