Design of 18-bit decimator for sigma-delta analog to digital converter with variable oversampling rate for audio application

An 18-bit decimator design for sigma-delta analog to digital converter with variable oversampling rate for audio application was successfully implemented in TSMC 0.13 um Logic CMOS Technology. Behavioral model of this project is implemented using MATLAB and actual implementation using RTL Code with the aid of Verilog Compiler Simulator. The oversampling rates used in this decimator design are 32, 64, 128 and 256. Also, this decimator uses 1 sinc filter and 2 halfband filters as the main blocks for the whole system. The result of the design actually minimized the delay of the signal as compared to the behavioral simulation obtained. The total cell area is reduced reaching the desirable signal-to-noise ratio.