verilog -基于氧化物的电阻随机存取存储器(RRAM)的紧凑型模型

2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) Pub Date : 2014-10-23 DOI:10.1109/SISPAD.2014.6931558

Zizhen Jiang, Shimeng Yu, Yi Wu, Jesse Engel, X. Guan, H. Wong

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引用次数: 111

摘要

我们展示了一个动态Verilog-A RRAM紧凑模型，能够模拟实时直流循环和脉冲操作设备的行为，包括RRAM固有的随机可变性。本文阐述了该模型的物理特性和性能。利用不同的实验数据对模型进行了验证。说明了直流/脉冲参数拟合方法。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Verilog-A compact model for oxide-based resistive random access memory (RRAM)

We demonstrate a dynamic Verilog-A RRAM compact model capable of simulating real-time DC cycling and pulsed operation device behavior, including random variability that is inherent to RRAM. This paper illustrates the physics and capabilities of the model. The model is verified using different sets of experimental data. The DC/Pulse parameter fitting methodology are illustrated.

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2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

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