基于空闲周期的RC6加密并发错误检测，[fpga]

Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2001-10-24 DOI:10.1109/DFTVS.2001.966771

Kaijie Wu, R. Karri

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引用次数: 14

摘要

描述一种并发错误检测(CED)技术，该技术使用数据路径中的空闲周期进行重新计算，并以RC6加密为例说明其优点和缺点。基于空闲周期的CED在保持强大的CED能力的同时具有较低的面积开销和性能损失。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Idle cycles based concurrent error detection of RC6 encryption, [FPGAs]

Describes a concurrent error detection (CED) technique that uses idle cycles in a data path to do the re-computation and demonstrate its benefits and drawbacks using RC6 encryption as a case study. The idle cycle based CED has low area overhead and performance penalty while maintaining strong CED capability.

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Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

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