{"title":"SOI四栅极晶体管(G4FET)的MOS-JFET宏模型以协助创新电路设计","authors":"Md. Sakib Hasan, I. Mahbub, S. Islam, G. Rose","doi":"10.1109/DCAS.2018.8620184","DOIUrl":null,"url":null,"abstract":"A MOS-JFET macromodel of silicon-on-insulator (SOI) four-gate transistor (G4FET) is presented in this paper to facilitate innovative circuit design with this novel multi-gate transistor. Designing interesting and innovative circuits with any new device requires a SPICE model that will work sufficiently well throughout the desired operating regions. A macromodel approach is adopted in this work which can provide a reasonably fast and accurate circuit simulation. Since G4FET combines the functionality of MOSFET and JFET devcies and robust, fast and reliable models of both MOSFET and JFET are already available, a macromodel combining these existing models is desirable from the perspective of a circuit designer. The model captures the essential interaction between multiple gates and accounts for both the volume and the surface conduction. In order to justify the feasibility of the macromodel, it is used to simulate two analog multiplier circuits which have been previously demonstrated experimentally and the simulation results match quite well with experimental findings.","PeriodicalId":320317,"journal":{"name":"2018 IEEE 13th Dallas Circuits and Systems Conference (DCAS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A MOS-JFET Macromodel of SOI Four-Gate Transistors (G4FET) to Aid Innovative Circuit Design\",\"authors\":\"Md. Sakib Hasan, I. Mahbub, S. Islam, G. Rose\",\"doi\":\"10.1109/DCAS.2018.8620184\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A MOS-JFET macromodel of silicon-on-insulator (SOI) four-gate transistor (G4FET) is presented in this paper to facilitate innovative circuit design with this novel multi-gate transistor. Designing interesting and innovative circuits with any new device requires a SPICE model that will work sufficiently well throughout the desired operating regions. A macromodel approach is adopted in this work which can provide a reasonably fast and accurate circuit simulation. Since G4FET combines the functionality of MOSFET and JFET devcies and robust, fast and reliable models of both MOSFET and JFET are already available, a macromodel combining these existing models is desirable from the perspective of a circuit designer. The model captures the essential interaction between multiple gates and accounts for both the volume and the surface conduction. In order to justify the feasibility of the macromodel, it is used to simulate two analog multiplier circuits which have been previously demonstrated experimentally and the simulation results match quite well with experimental findings.\",\"PeriodicalId\":320317,\"journal\":{\"name\":\"2018 IEEE 13th Dallas Circuits and Systems Conference (DCAS)\",\"volume\":\"24 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE 13th Dallas Circuits and Systems Conference (DCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DCAS.2018.8620184\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE 13th Dallas Circuits and Systems Conference (DCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DCAS.2018.8620184","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A MOS-JFET Macromodel of SOI Four-Gate Transistors (G4FET) to Aid Innovative Circuit Design
A MOS-JFET macromodel of silicon-on-insulator (SOI) four-gate transistor (G4FET) is presented in this paper to facilitate innovative circuit design with this novel multi-gate transistor. Designing interesting and innovative circuits with any new device requires a SPICE model that will work sufficiently well throughout the desired operating regions. A macromodel approach is adopted in this work which can provide a reasonably fast and accurate circuit simulation. Since G4FET combines the functionality of MOSFET and JFET devcies and robust, fast and reliable models of both MOSFET and JFET are already available, a macromodel combining these existing models is desirable from the perspective of a circuit designer. The model captures the essential interaction between multiple gates and accounts for both the volume and the surface conduction. In order to justify the feasibility of the macromodel, it is used to simulate two analog multiplier circuits which have been previously demonstrated experimentally and the simulation results match quite well with experimental findings.