基于fpga的加密数据同态计算高性能并行架构

S. Roy, Furkan Turan, K. Järvinen, F. Vercauteren, I. Verbauwhede
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引用次数: 127

摘要

同态加密是一种能够对加密数据进行计算的工具,因此在保护隐私的云计算中有应用。虽然同态加密的实现在概念上很神奇,但它非常具有挑战性,而且在通用计算机上的软件实现通常非常缓慢。在本文中,我们展示了我们一年来在异构Arm+FPGA平台上设计特定领域架构的努力,以加速对加密数据的同态计算。我们设计了一个定制的协处理器,用于FPGA上著名的Fan-Vercauteren (FV)同态加密方案的计算昂贵的操作,并使用基于FPGA的协处理器使Arm处理器成为在云中执行不同同态应用程序的服务器。我们使用最新的算法和算法优化技术,并在实现层次的不同层次上进行设计空间探索。特别地,我们应用电路级和块级管道策略分别提高时钟频率和提高吞吐量。为了减少计算延迟,我们在所有级别上使用并行处理。从高度优化的构建模块开始,我们逐步构建我们的多核多处理器计算架构。我们在单个Xilinx Zynq UltraScale+ MPSoC ZCU102评估套件上实现并测试了我们优化的特定领域可编程架构。在200 MHz fpga时钟下,我们的实现实现了超过13倍的加速,相对于在1.8 GHz运行的Intel i5处理器上高度优化的FV同态加密方案的软件实现。
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FPGA-Based High-Performance Parallel Architecture for Homomorphic Computing on Encrypted Data
—Homomorphic encryption is a tool that enables computation on encrypted data and thus has applications in privacy-preserving cloud computing. Though conceptually amaz- ing, implementation of homomorphic encryption is very challeng-ing and typically software implementations on general purpose computers are extremely slow. In this paper we present our year long effort to design a domain specific architecture in a heterogeneous Arm+FPGA platform to accelerate homomorphic computing on encrypted data. We design a custom co-processor for the computationally expensive operations of the well-known Fan-Vercauteren (FV) homomorphic encryption scheme on the FPGA, and make the Arm processor a server for executing different homomorphic applications in the cloud, using this FPGA-based co-processor. We use the most recent arithmetic and algorithmic optimization techniques and perform design- space exploration on different levels of the implementation hierarchy. In particular we apply circuit-level and block-level pipeline strategies to boost the clock frequency and increase the throughput respectively. To reduce computation latency, we use parallel processing at all levels. Starting from the highly optimized building blocks, we gradually build our multi-core multi-processor architecture for computing. We implemented and tested our optimized domain specific programmable architecture on a single Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit. At 200 MHz FPGA-clock, our implementation achieves over 13x speedup with respect to a highly optimized software implementation of the FV homomorphic encryption scheme on an Intel i5 processor running at 1.8 GHz.
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