65纳米CMOS技术下射频无源器件的建模与表征

E. Lourandakis, S. Stefanou, K. Nikellis, S. Bantas
{"title":"65纳米CMOS技术下射频无源器件的建模与表征","authors":"E. Lourandakis, S. Stefanou, K. Nikellis, S. Bantas","doi":"10.1109/ISQED.2013.6523680","DOIUrl":null,"url":null,"abstract":"Rapid passive device modeling is discussed in this work based on test structures fabricated in a 65nm CMOS process with M1-M9 copper metal layers and one aluminum metal layer AP. Capacitance extraction for overlapping microstrips and shielded microstrip structures is investigated. Individual capacitances are modeled in terms of area and fringe components, either between microstrips or between microstrips and silicon substrate. Good correlation to silicon data is achieved for the fabricated test structures. The validity of the proposed model is also investigated for complex passive devices such as inductors and interdigitated capacitors. Device metrics for both types of passive devices are investigated and compared to measured silicon data. Good agreement is achieved in all cases proving the accuracy of the proposed modeling approach.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"RF passive device modeling and characterization in 65nm CMOS technology\",\"authors\":\"E. Lourandakis, S. Stefanou, K. Nikellis, S. Bantas\",\"doi\":\"10.1109/ISQED.2013.6523680\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Rapid passive device modeling is discussed in this work based on test structures fabricated in a 65nm CMOS process with M1-M9 copper metal layers and one aluminum metal layer AP. Capacitance extraction for overlapping microstrips and shielded microstrip structures is investigated. Individual capacitances are modeled in terms of area and fringe components, either between microstrips or between microstrips and silicon substrate. Good correlation to silicon data is achieved for the fabricated test structures. The validity of the proposed model is also investigated for complex passive devices such as inductors and interdigitated capacitors. Device metrics for both types of passive devices are investigated and compared to measured silicon data. Good agreement is achieved in all cases proving the accuracy of the proposed modeling approach.\",\"PeriodicalId\":127115,\"journal\":{\"name\":\"International Symposium on Quality Electronic Design (ISQED)\",\"volume\":\"53 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-03-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Symposium on Quality Electronic Design (ISQED)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISQED.2013.6523680\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Symposium on Quality Electronic Design (ISQED)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISQED.2013.6523680","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6

摘要

本文讨论了基于65nm CMOS工艺制备的M1-M9铜金属层和1铝金属层AP的测试结构的快速无源器件建模,并研究了重叠微带和屏蔽微带结构的电容提取。在微带之间或微带与硅衬底之间,单个电容根据面积和条纹分量进行建模。制备的测试结构与硅数据具有良好的相关性。本文还对电感和交叉电容等复杂无源器件的有效性进行了研究。研究了两种无源器件的器件指标,并将其与测量的硅数据进行了比较。在所有情况下都取得了良好的一致性,证明了所提出的建模方法的准确性。
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RF passive device modeling and characterization in 65nm CMOS technology
Rapid passive device modeling is discussed in this work based on test structures fabricated in a 65nm CMOS process with M1-M9 copper metal layers and one aluminum metal layer AP. Capacitance extraction for overlapping microstrips and shielded microstrip structures is investigated. Individual capacitances are modeled in terms of area and fringe components, either between microstrips or between microstrips and silicon substrate. Good correlation to silicon data is achieved for the fabricated test structures. The validity of the proposed model is also investigated for complex passive devices such as inductors and interdigitated capacitors. Device metrics for both types of passive devices are investigated and compared to measured silicon data. Good agreement is achieved in all cases proving the accuracy of the proposed modeling approach.
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