{"title":"用于模拟MOS电路的基于堆栈的模块发生器","authors":"S. Spanoche, G. B. Arsintescu","doi":"10.1109/SMICND.1996.557324","DOIUrl":null,"url":null,"abstract":"This paper describes a novel method for analog circuit partitioning and MOS transistor stacking. The method is based on a new algorithm dealing with analog specific constraints and on a set of heuristics for stack generation using a pattern database and transistor size trimming. Experimental results show the effectiveness of the method that is described.","PeriodicalId":266178,"journal":{"name":"1996 International Semiconductor Conference. 19th Edition. CAS'96 Proceedings","volume":"100 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Stack based module generator for analog MOS circuits\",\"authors\":\"S. Spanoche, G. B. Arsintescu\",\"doi\":\"10.1109/SMICND.1996.557324\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes a novel method for analog circuit partitioning and MOS transistor stacking. The method is based on a new algorithm dealing with analog specific constraints and on a set of heuristics for stack generation using a pattern database and transistor size trimming. Experimental results show the effectiveness of the method that is described.\",\"PeriodicalId\":266178,\"journal\":{\"name\":\"1996 International Semiconductor Conference. 19th Edition. CAS'96 Proceedings\",\"volume\":\"100 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-10-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1996 International Semiconductor Conference. 19th Edition. CAS'96 Proceedings\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SMICND.1996.557324\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1996 International Semiconductor Conference. 19th Edition. CAS'96 Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SMICND.1996.557324","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Stack based module generator for analog MOS circuits
This paper describes a novel method for analog circuit partitioning and MOS transistor stacking. The method is based on a new algorithm dealing with analog specific constraints and on a set of heuristics for stack generation using a pattern database and transistor size trimming. Experimental results show the effectiveness of the method that is described.
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