基于65nm CMOS的3位20gs /s ADC设计

2009 Ph.D. Research in Microelectronics and Electronics Pub Date : 2009-07-12 DOI:10.1109/RME.2009.5201305

D. Ferenci, M. Grozing, M. Berroth

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引用次数: 7

摘要

采用65nm LP CMOS技术实现了模拟输入带宽为10ghz的20gs /s 3位闪存ADC。通过采用四倍并行，实现了高采样率，同时保持了大的输入带宽。在20gs /s的模拟中，奈奎斯特频率下的有效分辨率为2.5比特。芯片面积为5.2mm2, ADC核心面积为0.16mm2。

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Design of a 3 Bit 20 GS/s ADC in 65 nm CMOS

A 20 GS/s 3 bit flash ADC with an analog input bandwidth of 10 GHz is realized in a 65nm LP CMOS technology. By employing a fourfold parallelization a high sample rate is achieved, while a large input bandwidth is maintained. Simulations at 20 GS/s exhibit an effective resolution of 2.5 Bits at the Nyquist frequency. The chip area is 5.2mm2 while the ADC core area is 0.16mm2.

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2009 Ph.D. Research in Microelectronics and Electronics

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