A Bayesian Optimization Framework for Analog Circuits Optimization

The growing complexity of analog circuits poses challenging constraints on analog simulation tools. Simulation based optimization approaches have gained a lot of interest to cut down the analog circuit design time and complexity. One of these approaches is the Bayesian optimization (BO) approach, which represents the analog circuit as a black box function, and incorporates optimization goal and constraints aiming to reach the optimum design parameters with the least possible simulation iterations. In this paper, a BO approach for automated sizing of analog circuits is discussed. The proposed approach uses Gaussian Process (GP) as a surrogate model and utilizes SOBOL sampling. The proposed algorithm is validated on a two-stage op amp benchmark circuit and compared to the literature work.