提出了一种新的钨塞腐蚀失效机制

S. Bothra, H. Sur, V. Liang
{"title":"提出了一种新的钨塞腐蚀失效机制","authors":"S. Bothra, H. Sur, V. Liang","doi":"10.1109/RELPHY.1998.670473","DOIUrl":null,"url":null,"abstract":"The tungsten filled via plug process is commonly used in sub-half micron CMOS process technologies. As process technologies shrink beyond the 0.25 /spl mu/m generation, the metal overlap over the via also reduces. This results in vias which are not fully covered by the overlying interconnect lines. In the evaluation of such structures, we have observed a new failure mechanism resulting in completely unfilled vias due to electrochemical corrosion accelerated by a positive charge on specific structures.","PeriodicalId":196556,"journal":{"name":"1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"28","resultStr":"{\"title\":\"A new failure mechanism by corrosion of tungsten in a tungsten plug process\",\"authors\":\"S. Bothra, H. Sur, V. Liang\",\"doi\":\"10.1109/RELPHY.1998.670473\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The tungsten filled via plug process is commonly used in sub-half micron CMOS process technologies. As process technologies shrink beyond the 0.25 /spl mu/m generation, the metal overlap over the via also reduces. This results in vias which are not fully covered by the overlying interconnect lines. In the evaluation of such structures, we have observed a new failure mechanism resulting in completely unfilled vias due to electrochemical corrosion accelerated by a positive charge on specific structures.\",\"PeriodicalId\":196556,\"journal\":{\"name\":\"1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173)\",\"volume\":\"5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"28\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RELPHY.1998.670473\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RELPHY.1998.670473","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 28

摘要

在亚半微米的CMOS工艺技术中,常用的是插塞填充钨。随着工艺技术的缩减超过0.25 /spl mu/m一代,通孔上的金属重叠也减少了。这导致过孔没有完全被覆盖的互连线覆盖。在对这种结构的评价中,我们观察到一种新的失效机制,由于特定结构上的正电荷加速了电化学腐蚀,导致了完全未填充的通孔。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
A new failure mechanism by corrosion of tungsten in a tungsten plug process
The tungsten filled via plug process is commonly used in sub-half micron CMOS process technologies. As process technologies shrink beyond the 0.25 /spl mu/m generation, the metal overlap over the via also reduces. This results in vias which are not fully covered by the overlying interconnect lines. In the evaluation of such structures, we have observed a new failure mechanism resulting in completely unfilled vias due to electrochemical corrosion accelerated by a positive charge on specific structures.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Stress-induced voiding in stacked tungsten via structure Dislocation dynamics in heterojunction bipolar transistor under current induced thermal stress Effect of H/sub 2/O partial pressure and temperature during Ti sputtering on texture and electromigration in AlSiCu-Ti-TiN-Ti metallization Backside localization of open and shorted IC interconnections Full-chip reliability analysis
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1