S. Ishiwata, T. Yamakage, Y. Tsuboi, T. Shimazawa, T. Kitazawa, Shuji Michinaka, Kunihiko Yahagi, Hideki Takeda, Akihiro Oue, T. Kodama, Nobu Matsumoto, Takayuki Kamei, T. Miyamori, G. Ootomo, M. Matsui
{"title":"基于可定制媒体微处理器的单片MPEG-2编解码器","authors":"S. Ishiwata, T. Yamakage, Y. Tsuboi, T. Shimazawa, T. Kitazawa, Shuji Michinaka, Kunihiko Yahagi, Hideki Takeda, Akihiro Oue, T. Kodama, Nobu Matsumoto, Takayuki Kamei, T. Miyamori, G. Ootomo, M. Matsui","doi":"10.1109/CICC.2002.1012789","DOIUrl":null,"url":null,"abstract":"A single-chip MPEG2 MP@ML codec, integrating 3.8M gates on a 72mm/sup 2/ die, is described. It has a heterogeneous multiprocessor architecture in which six microprocessors with the same instruction set but different customization execute specific tasks such as video, audio etc. concurrently. The microprocessor, developed for digital media processing, provides various extensions such as a VLIW one and a DSP one inherent in its architecture. Making full use of the extensions, the chip executes encoding and decoding of video, audio and system concurrently in real time.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":"{\"title\":\"A single-chip MPEG-2 codec based on customizable media microprocessor\",\"authors\":\"S. Ishiwata, T. Yamakage, Y. Tsuboi, T. Shimazawa, T. Kitazawa, Shuji Michinaka, Kunihiko Yahagi, Hideki Takeda, Akihiro Oue, T. Kodama, Nobu Matsumoto, Takayuki Kamei, T. Miyamori, G. Ootomo, M. Matsui\",\"doi\":\"10.1109/CICC.2002.1012789\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A single-chip MPEG2 MP@ML codec, integrating 3.8M gates on a 72mm/sup 2/ die, is described. It has a heterogeneous multiprocessor architecture in which six microprocessors with the same instruction set but different customization execute specific tasks such as video, audio etc. concurrently. The microprocessor, developed for digital media processing, provides various extensions such as a VLIW one and a DSP one inherent in its architecture. Making full use of the extensions, the chip executes encoding and decoding of video, audio and system concurrently in real time.\",\"PeriodicalId\":209025,\"journal\":{\"name\":\"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)\",\"volume\":\"18 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"12\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2002.1012789\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2002.1012789","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A single-chip MPEG-2 codec based on customizable media microprocessor
A single-chip MPEG2 MP@ML codec, integrating 3.8M gates on a 72mm/sup 2/ die, is described. It has a heterogeneous multiprocessor architecture in which six microprocessors with the same instruction set but different customization execute specific tasks such as video, audio etc. concurrently. The microprocessor, developed for digital media processing, provides various extensions such as a VLIW one and a DSP one inherent in its architecture. Making full use of the extensions, the chip executes encoding and decoding of video, audio and system concurrently in real time.
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