Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI Interconnects

Process variations can have a significant impact on both device and interconnect performance in deep sub-micron (DSM) technology. In this paper, initially authors discuss the effects of process parameter variations on bus-encoding schemes for delay minimization in VLSI interconnects. Later, process variation aware bus-coding scheme is proposed to reduce delay in interconnects. It is shown that if process variability is taken into consideration, effective capacitance (Ceff) of the bus lines varies because of which the amount of delay that each crosstalk class causes is going to vary. SPICE simulations have been carried out for interconnect lines of different dimensions at different technology nodes (180, 130, 90 and 65 nm) to find out the effect of process variation on the effective capacitance of bus lines and to evaluate the percentage delay reduction due to proposed coding scheme.