Qi Zhang, Ning Wang, D. Yuan, Guohong Li, Hui Wang, Songlin Feng
{"title":"低功耗可重构GFSK射频收发器与低于1ghz频段的短距离应用","authors":"Qi Zhang, Ning Wang, D. Yuan, Guohong Li, Hui Wang, Songlin Feng","doi":"10.1109/ICECS.2013.6815502","DOIUrl":null,"url":null,"abstract":"A fully-integrated reconfigurable RF transceiver dedicated for the sub-1GHz short range wireless applications is presented. The RF transceiver mainly consists of a reconfigurable RF front-end, a low-power reconfigurable receiver IF part and a Σ-Δ fractional-N PLL. The RF front-end with highly switchable gain/NF/output power with broadband matching for sub-1GHz frequency is proposed. The polyphase filter (PPF) with independently reconfigurable center frequency/bandwidth/gain is proposed for different protocols. GFSK modulation format is adopted at data rates from 250Kbps to 2Mbps. The chip is implemented in 0.18um CMOS process. Operating in the typical 400MHz band with 2Mbps data rate, the receiver consumes 9.5mA from a 1.8V supply and achieves a sensitivity of -87dBm with 0.1% BER. The transmitter consumes 12mA for an output power of +3dBm.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"314 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A low-power reconfigurable GFSK RF transceiver with sub-1GHz band for short range applications\",\"authors\":\"Qi Zhang, Ning Wang, D. Yuan, Guohong Li, Hui Wang, Songlin Feng\",\"doi\":\"10.1109/ICECS.2013.6815502\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A fully-integrated reconfigurable RF transceiver dedicated for the sub-1GHz short range wireless applications is presented. The RF transceiver mainly consists of a reconfigurable RF front-end, a low-power reconfigurable receiver IF part and a Σ-Δ fractional-N PLL. The RF front-end with highly switchable gain/NF/output power with broadband matching for sub-1GHz frequency is proposed. The polyphase filter (PPF) with independently reconfigurable center frequency/bandwidth/gain is proposed for different protocols. GFSK modulation format is adopted at data rates from 250Kbps to 2Mbps. The chip is implemented in 0.18um CMOS process. Operating in the typical 400MHz band with 2Mbps data rate, the receiver consumes 9.5mA from a 1.8V supply and achieves a sensitivity of -87dBm with 0.1% BER. The transmitter consumes 12mA for an output power of +3dBm.\",\"PeriodicalId\":117453,\"journal\":{\"name\":\"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)\",\"volume\":\"314 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICECS.2013.6815502\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2013.6815502","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A low-power reconfigurable GFSK RF transceiver with sub-1GHz band for short range applications
A fully-integrated reconfigurable RF transceiver dedicated for the sub-1GHz short range wireless applications is presented. The RF transceiver mainly consists of a reconfigurable RF front-end, a low-power reconfigurable receiver IF part and a Σ-Δ fractional-N PLL. The RF front-end with highly switchable gain/NF/output power with broadband matching for sub-1GHz frequency is proposed. The polyphase filter (PPF) with independently reconfigurable center frequency/bandwidth/gain is proposed for different protocols. GFSK modulation format is adopted at data rates from 250Kbps to 2Mbps. The chip is implemented in 0.18um CMOS process. Operating in the typical 400MHz band with 2Mbps data rate, the receiver consumes 9.5mA from a 1.8V supply and achieves a sensitivity of -87dBm with 0.1% BER. The transmitter consumes 12mA for an output power of +3dBm.