S. Tsuda, T. Saito, H. Nagase, Y. Kawashima, A. Yoshitomi, S. Okanishi, T. Hayashi, T. Maruyama, M. Inoue, S. Muranaka, S. Kato, T. Hagiwara, H. Saito, T. Yamaguchi, M. Kadoshima, T. Mihara, H. Yanagita, K. Sonoda, T. Yamashita, Y. Yamaguchi
{"title":"16/14nm节点嵌入式闪存紧v分布FinFET分栅MONOS阵列的可靠性和可扩展性","authors":"S. Tsuda, T. Saito, H. Nagase, Y. Kawashima, A. Yoshitomi, S. Okanishi, T. Hayashi, T. Maruyama, M. Inoue, S. Muranaka, S. Kato, T. Hagiwara, H. Saito, T. Yamaguchi, M. Kadoshima, T. Mihara, H. Yanagita, K. Sonoda, T. Yamashita, Y. Yamaguchi","doi":"10.1109/IEDM.2017.8268421","DOIUrl":null,"url":null,"abstract":"Reliability and scalability of split-gate metal-oxide nitride oxide silicon (SG-MONOS) are discussed for 16/14nm-node embedded Flash in FinFET-era. FinFET SG-MONOS array is successfully operated with wide enough program/erase window. The Vth distribution of FinFET SG-MONOS array is kept tighter than planar even after retention. It is also demonstrated that Fin structure enables scaling of the control gate and the memory gate, which leads to the improvement of retention characteristics due to reduction of the mismatch of trapped carrier distribution during program/erase operation.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Reliability and scalability of FinFET split-gate MONOS array with tight Vth distribution for 16/14nm-node embedded flash\",\"authors\":\"S. Tsuda, T. Saito, H. Nagase, Y. Kawashima, A. Yoshitomi, S. Okanishi, T. Hayashi, T. Maruyama, M. Inoue, S. Muranaka, S. Kato, T. Hagiwara, H. Saito, T. Yamaguchi, M. Kadoshima, T. Mihara, H. Yanagita, K. Sonoda, T. Yamashita, Y. Yamaguchi\",\"doi\":\"10.1109/IEDM.2017.8268421\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Reliability and scalability of split-gate metal-oxide nitride oxide silicon (SG-MONOS) are discussed for 16/14nm-node embedded Flash in FinFET-era. FinFET SG-MONOS array is successfully operated with wide enough program/erase window. The Vth distribution of FinFET SG-MONOS array is kept tighter than planar even after retention. It is also demonstrated that Fin structure enables scaling of the control gate and the memory gate, which leads to the improvement of retention characteristics due to reduction of the mismatch of trapped carrier distribution during program/erase operation.\",\"PeriodicalId\":412333,\"journal\":{\"name\":\"2017 IEEE International Electron Devices Meeting (IEDM)\",\"volume\":\"84 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 IEEE International Electron Devices Meeting (IEDM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2017.8268421\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE International Electron Devices Meeting (IEDM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2017.8268421","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Reliability and scalability of FinFET split-gate MONOS array with tight Vth distribution for 16/14nm-node embedded flash
Reliability and scalability of split-gate metal-oxide nitride oxide silicon (SG-MONOS) are discussed for 16/14nm-node embedded Flash in FinFET-era. FinFET SG-MONOS array is successfully operated with wide enough program/erase window. The Vth distribution of FinFET SG-MONOS array is kept tighter than planar even after retention. It is also demonstrated that Fin structure enables scaling of the control gate and the memory gate, which leads to the improvement of retention characteristics due to reduction of the mismatch of trapped carrier distribution during program/erase operation.
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