{"title":"砷化镓施密特触发存储单元设计","authors":"O.M.K. Law, C. Salama","doi":"10.1109/GAAS.1993.394494","DOIUrl":null,"url":null,"abstract":"A GaAs five-transistor static memory cell is proposed. It is derived from nMOS Schmitt trigger. The memory cell overcomes the subthreshold leakage loss by using a self ground-shifting technique which limits the leakage current flow to the cell. Compared with conventional GaAs SRAM cells, it offers small design area and allows large memory arrays to be realized. A prototype was implemented in a 1 /spl mu/m non-self aligned GaAs MESFET technology with read and write access time of 1.0 ns and 1.25 ns, respectively.<<ETX>>","PeriodicalId":347339,"journal":{"name":"15th Annual GaAs IC Symposium","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"GaAs Schmitt trigger memory cell design\",\"authors\":\"O.M.K. Law, C. Salama\",\"doi\":\"10.1109/GAAS.1993.394494\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A GaAs five-transistor static memory cell is proposed. It is derived from nMOS Schmitt trigger. The memory cell overcomes the subthreshold leakage loss by using a self ground-shifting technique which limits the leakage current flow to the cell. Compared with conventional GaAs SRAM cells, it offers small design area and allows large memory arrays to be realized. A prototype was implemented in a 1 /spl mu/m non-self aligned GaAs MESFET technology with read and write access time of 1.0 ns and 1.25 ns, respectively.<<ETX>>\",\"PeriodicalId\":347339,\"journal\":{\"name\":\"15th Annual GaAs IC Symposium\",\"volume\":\"24 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-10-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"15th Annual GaAs IC Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/GAAS.1993.394494\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"15th Annual GaAs IC Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GAAS.1993.394494","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A GaAs five-transistor static memory cell is proposed. It is derived from nMOS Schmitt trigger. The memory cell overcomes the subthreshold leakage loss by using a self ground-shifting technique which limits the leakage current flow to the cell. Compared with conventional GaAs SRAM cells, it offers small design area and allows large memory arrays to be realized. A prototype was implemented in a 1 /spl mu/m non-self aligned GaAs MESFET technology with read and write access time of 1.0 ns and 1.25 ns, respectively.<>
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