{"title":"基于改进色散延迟线(DDL)的集成ku波段纳秒时延系统","authors":"Bo Xiang, A. Kopa, Zhongtao Fu, A. Apsel","doi":"10.1109/SIRF.2012.6160140","DOIUrl":null,"url":null,"abstract":"In this paper, we report an on-chip implementation of a Ku-band nanosecond scale time-stretching (TS) system in a 130 nm CMOS process. The system employs a linear chirp generator realized by ramping the control voltage of the voltage controlled oscillator (VCO), a broadband amplitude modulation (AM) circuit and an active dispersive delay line (DDL) improved from a previous integrated DDL, showing 1 ns dispersion over the frequency range from 12 GHz to 16 GHz. This work not only shows the experimental demonstration of the time stretching effect on the pulsed signal, but also indicates the potential for implementation of more complicated time scaling signal processing systems on chip.","PeriodicalId":339730,"journal":{"name":"2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"An integrated Ku-band nanosecond time-stretching system using improved dispersive delay line (DDL)\",\"authors\":\"Bo Xiang, A. Kopa, Zhongtao Fu, A. Apsel\",\"doi\":\"10.1109/SIRF.2012.6160140\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we report an on-chip implementation of a Ku-band nanosecond scale time-stretching (TS) system in a 130 nm CMOS process. The system employs a linear chirp generator realized by ramping the control voltage of the voltage controlled oscillator (VCO), a broadband amplitude modulation (AM) circuit and an active dispersive delay line (DDL) improved from a previous integrated DDL, showing 1 ns dispersion over the frequency range from 12 GHz to 16 GHz. This work not only shows the experimental demonstration of the time stretching effect on the pulsed signal, but also indicates the potential for implementation of more complicated time scaling signal processing systems on chip.\",\"PeriodicalId\":339730,\"journal\":{\"name\":\"2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-03-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SIRF.2012.6160140\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SIRF.2012.6160140","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An integrated Ku-band nanosecond time-stretching system using improved dispersive delay line (DDL)
In this paper, we report an on-chip implementation of a Ku-band nanosecond scale time-stretching (TS) system in a 130 nm CMOS process. The system employs a linear chirp generator realized by ramping the control voltage of the voltage controlled oscillator (VCO), a broadband amplitude modulation (AM) circuit and an active dispersive delay line (DDL) improved from a previous integrated DDL, showing 1 ns dispersion over the frequency range from 12 GHz to 16 GHz. This work not only shows the experimental demonstration of the time stretching effect on the pulsed signal, but also indicates the potential for implementation of more complicated time scaling signal processing systems on chip.