An Efficient Timing Model of Flip-Flops Based on Artificial Neural Network

Traditionally, the timing model of a flip-flop in the technology libraries captures the setup time (ST), hold time (HT) and clock-to-q (C2Q) delays in separate two-dimensional lookup tables. However, it is well-known that these attributes of flip-flops are interdependent. By modeling them separately we introduce pessimism in the design flows. In this paper, we represent the C2Q delays of a flip-flop using artificial neural networks (ANN) and store them in technology libraries. The ANN captures the dependency of the C2Q delay on the data slew, clock slew, output load, setup skew and hold skew. We show that the proposed model computes the C2Q delays with errors less than 3% compared to the SPICE model. Furthermore, using 65 nm foundry library and 15 nm NCSU FreePDK15 models, we demonstrate the effectiveness of the proposed model in removing pessimism of the traditional flip-flop timing model. Additionally, we can employ it to transfer the surplus slack on the output side of a flip-flop to the input side. Thus, we can filter out marginal timing violations and alleviate the timing closure problem using the proposed model.