A 12.5-Gb/s 4.8-mW Full-Rate CDR with Low-Power Sample-and-Hold Linear Phase Detector

This paper presents a low-power low-jitter full-rate linear phase detector based clock and data recovery circuit (CDR). The proposed sample-and-hold linear phase detector (SHLPD) can reduce the complexity of the conventional SHLPD to save power consumption. This CDR is designed and implemented in 40-nm CMOS process with 0.9-V supply. The simulation results show that it can operate at data rate of 12.5 Gb/s with the power consumption of 4.8 mW. The simulated peak-to-peak jitter of the recovered data and clock is 4.96 ps and 4.64 ps, respectively, with 12.5-Gb/s input data rate.