VC生成器的形式化模型验证

R. Arthan
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引用次数: 0

摘要

本文描述了为了解Ada验证系统而进行的一些建模工作。它在Z中给出了一个简单的形式模型,该模型是一种细化表示法,它包括一个用形式规范注释的微型但完整的命令式编程语言。定义了该编程语言的语义和相对于规范注释的正确性概念。给出了验证条件生成器的语义模型,该模型在编程语言语义和规范注释的内涵语义两方面都是可靠的。规格书和校样是使用校样系统编写的,所有校样都经过了全面的机器检查。我们认为,使用适当的抽象和良好的工具,使机器检验证明成为一个现实和有益的目标
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A Verified Formal Model of a VC Generator
This paper describes some modelling work carried out to inform understanding of an Ada verification system. It presents a simple formal model in Z of a refinement notation comprising a miniature, but complete, imperative programming language annotated with formal specifications. The semantics of that programming language and the notion of correctness relative to the specification annotations is defined. A semantic model of a verification condition generator is given which can be proved to be sound with respect both to the programming language semantics and to the intensional semantics of the specification annotations. The specifications and proofs were prepared using the proofpower system and all proofs have been fully machine-checked. We argue that the use of appropriate abstractions and good tools make machine-checked proof a realistic and beneficial target
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