{"title":"用于SoC应用的单输入双输出三电平降压转换器","authors":"Zhuoneng Li, Zhonamina Xue, Chenalona Liang, Yongchao Zhang, Mengqi Duan, Shangzhou Zhao, Xihao Liu, Zhuoqi Guo, Li Geng","doi":"10.1109/ICTA56932.2022.9963024","DOIUrl":null,"url":null,"abstract":"This paper proposes a single-input dual-output (SIDO) three-level buck converter to meet the requirements of multi-voltage domain and high voltage stress for SoC applications. The topology is based on three-level buck with standard 1.8V devices, where only an additional power switch is added. By using this structure, the second output can be powered by a fly capacitor, and $V$CF calibration is achieved by the control loop for reliability issues. Hence the efficiency and the power density are enhanced with standard devices and reducing the number of power switches. Moreover, the control loop with error processor and driver module is demonstrated based on the topology analysis. Ultimately, the proposed converter is designed and fabricated with 0.18μm CMOS process, which handles the input range of 3.3-2.8V and dual-output of 1.8V and 1.2V with 96.9% peak efficiency. The power density is 2.557W/mm2, and the active area is only 0.49 mm2.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Single-input Dual-output Three-level Buck Converter for SoC Applications\",\"authors\":\"Zhuoneng Li, Zhonamina Xue, Chenalona Liang, Yongchao Zhang, Mengqi Duan, Shangzhou Zhao, Xihao Liu, Zhuoqi Guo, Li Geng\",\"doi\":\"10.1109/ICTA56932.2022.9963024\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes a single-input dual-output (SIDO) three-level buck converter to meet the requirements of multi-voltage domain and high voltage stress for SoC applications. The topology is based on three-level buck with standard 1.8V devices, where only an additional power switch is added. By using this structure, the second output can be powered by a fly capacitor, and $V$CF calibration is achieved by the control loop for reliability issues. Hence the efficiency and the power density are enhanced with standard devices and reducing the number of power switches. Moreover, the control loop with error processor and driver module is demonstrated based on the topology analysis. Ultimately, the proposed converter is designed and fabricated with 0.18μm CMOS process, which handles the input range of 3.3-2.8V and dual-output of 1.8V and 1.2V with 96.9% peak efficiency. The power density is 2.557W/mm2, and the active area is only 0.49 mm2.\",\"PeriodicalId\":325602,\"journal\":{\"name\":\"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)\",\"volume\":\"4 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-10-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICTA56932.2022.9963024\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICTA56932.2022.9963024","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Single-input Dual-output Three-level Buck Converter for SoC Applications
This paper proposes a single-input dual-output (SIDO) three-level buck converter to meet the requirements of multi-voltage domain and high voltage stress for SoC applications. The topology is based on three-level buck with standard 1.8V devices, where only an additional power switch is added. By using this structure, the second output can be powered by a fly capacitor, and $V$CF calibration is achieved by the control loop for reliability issues. Hence the efficiency and the power density are enhanced with standard devices and reducing the number of power switches. Moreover, the control loop with error processor and driver module is demonstrated based on the topology analysis. Ultimately, the proposed converter is designed and fabricated with 0.18μm CMOS process, which handles the input range of 3.3-2.8V and dual-output of 1.8V and 1.2V with 96.9% peak efficiency. The power density is 2.557W/mm2, and the active area is only 0.49 mm2.