用于SoC应用的单输入双输出三电平降压转换器

Zhuoneng Li, Zhonamina Xue, Chenalona Liang, Yongchao Zhang, Mengqi Duan, Shangzhou Zhao, Xihao Liu, Zhuoqi Guo, Li Geng
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引用次数: 0

摘要

为了满足SoC应用中多电压域和高电压应力的要求,提出了一种单输入双输出(SIDO)三电平降压变换器。该拓扑基于标准1.8V器件的三电平降压,其中只增加了一个额外的电源开关。通过使用这种结构,第二个输出可以由飞电容供电,并且通过控制回路实现$V$CF校准,以解决可靠性问题。因此,采用标准器件提高了效率和功率密度,并减少了功率开关的数量。在拓扑分析的基础上,给出了带有误差处理器和驱动模块的控制回路。最后,采用0.18μm CMOS工艺设计制作了该变换器,其输入范围为3.3 ~ 2.8 v,双输出1.8V和1.2V,峰值效率为96.9%。功率密度为2.557W/mm2,有源面积仅为0.49 mm2。
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A Single-input Dual-output Three-level Buck Converter for SoC Applications
This paper proposes a single-input dual-output (SIDO) three-level buck converter to meet the requirements of multi-voltage domain and high voltage stress for SoC applications. The topology is based on three-level buck with standard 1.8V devices, where only an additional power switch is added. By using this structure, the second output can be powered by a fly capacitor, and $V$CF calibration is achieved by the control loop for reliability issues. Hence the efficiency and the power density are enhanced with standard devices and reducing the number of power switches. Moreover, the control loop with error processor and driver module is demonstrated based on the topology analysis. Ultimately, the proposed converter is designed and fabricated with 0.18μm CMOS process, which handles the input range of 3.3-2.8V and dual-output of 1.8V and 1.2V with 96.9% peak efficiency. The power density is 2.557W/mm2, and the active area is only 0.49 mm2.
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