{"title":"用于10位5-Msamples/Sec流水线ADC的伪反转采样保持电路设计","authors":"M. Santosh, K. C. Behera, S. Bose","doi":"10.1109/ELECTRO.2009.5441162","DOIUrl":null,"url":null,"abstract":"This paper describes the design of a pseudo flip-around sample- hold circuit for a 10-bit, 5-Msamples/sec pipeline ADC. The sample-hold circuit is simulated in 0.35 µm Austria Microsystems technology with a 1 KHz, 1.2 Vp-p sinusoidal input and a sampling clock of 5 MHz. The simulation shows a worst case sampling error of 1mV, SNR of 60dB. The layout of the sample hold circuit occupies an area of 0.007mm2 and consumes 1.7 mW of power.","PeriodicalId":149384,"journal":{"name":"2009 International Conference on Emerging Trends in Electronic and Photonic Devices & Systems","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design of pseudo flip-around sample hold- circuit for 10-bit, 5-Msamples/Sec pipeline ADC\",\"authors\":\"M. Santosh, K. C. Behera, S. Bose\",\"doi\":\"10.1109/ELECTRO.2009.5441162\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes the design of a pseudo flip-around sample- hold circuit for a 10-bit, 5-Msamples/sec pipeline ADC. The sample-hold circuit is simulated in 0.35 µm Austria Microsystems technology with a 1 KHz, 1.2 Vp-p sinusoidal input and a sampling clock of 5 MHz. The simulation shows a worst case sampling error of 1mV, SNR of 60dB. The layout of the sample hold circuit occupies an area of 0.007mm2 and consumes 1.7 mW of power.\",\"PeriodicalId\":149384,\"journal\":{\"name\":\"2009 International Conference on Emerging Trends in Electronic and Photonic Devices & Systems\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 International Conference on Emerging Trends in Electronic and Photonic Devices & Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ELECTRO.2009.5441162\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Conference on Emerging Trends in Electronic and Photonic Devices & Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ELECTRO.2009.5441162","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of pseudo flip-around sample hold- circuit for 10-bit, 5-Msamples/Sec pipeline ADC
This paper describes the design of a pseudo flip-around sample- hold circuit for a 10-bit, 5-Msamples/sec pipeline ADC. The sample-hold circuit is simulated in 0.35 µm Austria Microsystems technology with a 1 KHz, 1.2 Vp-p sinusoidal input and a sampling clock of 5 MHz. The simulation shows a worst case sampling error of 1mV, SNR of 60dB. The layout of the sample hold circuit occupies an area of 0.007mm2 and consumes 1.7 mW of power.
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