Latency tolerance techniques for real-time ray tracing on mobile computing platform

In this paper, we propose an efficient ray scheduling algorithm and non-block cache architecture to hiding main-memory access latency targeting real-time ray tracing on mobile device. We first analyze on the impact of a memory latency by analyzing the memory access patterns for a ray tracing system and present a novel ray scheduling method using a non-block pipeline feedback and cache architecture for ray tracing hardware engine. To achieve more cache efficiency, we also present a memory-efficient encoding scheme for the scene geometry. For an evaluation of our approach, we implemented a prototype ray tracing architecture using our approach on an FPGA platform. Our experimental results indicate that our approach shows that an average performance conservation of 85% and an average performance improves of 2.4 times.