{"title":"MOS数字单元的布局合成","authors":"A. Domic","doi":"10.1109/DAC.1990.114861","DOIUrl":null,"url":null,"abstract":"The main issues specific to the cell generation of MOS digital circuits are reviewed. The discussion concentrates on the direct use of arbitrary cells, or the quick generation of new library items, rather than the application of general place and route algorithms. Specifically, transistor ordering for Boolean gates, routing a cell, and polygon generation are discussed.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Layout synthesis of MOS digital cells\",\"authors\":\"A. Domic\",\"doi\":\"10.1109/DAC.1990.114861\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The main issues specific to the cell generation of MOS digital circuits are reviewed. The discussion concentrates on the direct use of arbitrary cells, or the quick generation of new library items, rather than the application of general place and route algorithms. Specifically, transistor ordering for Boolean gates, routing a cell, and polygon generation are discussed.<<ETX>>\",\"PeriodicalId\":118552,\"journal\":{\"name\":\"27th ACM/IEEE Design Automation Conference\",\"volume\":\"25 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-06-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"27th ACM/IEEE Design Automation Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DAC.1990.114861\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"27th ACM/IEEE Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DAC.1990.114861","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The main issues specific to the cell generation of MOS digital circuits are reviewed. The discussion concentrates on the direct use of arbitrary cells, or the quick generation of new library items, rather than the application of general place and route algorithms. Specifically, transistor ordering for Boolean gates, routing a cell, and polygon generation are discussed.<>
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