采用7层金属0.11 /spl mu/m CMOS技术的8路VLIW嵌入式多媒体处理器

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI:10.1109/ISSCC.2002.992265

H. Okano, A. Suga, T. Shiota, Y. Takebe, Yasuki Nakamura, N. Higaki, Haruo Kimura, H. Miyake, T. Satoh, K. Kawasaki, R. Sasagawa, W. Shibamoto, Mitsuru Sasaki, Naruyoshi Ando, Tomohiro Yamana, I. Fukushi, S. Tago, F. Hayakawa, Teruhiko Kamigata, S. Imai, Atsushi Satoh, Yasuaki Hatta, Noboru Nishimura, Y. Asada, Taizo Satoh, Takao Sukemura, S. Ando, Hiromasa Takahashi

{"title":"采用7层金属0.11 /spl mu/m CMOS技术的8路VLIW嵌入式多媒体处理器","authors":"H. Okano, A. Suga, T. Shiota, Y. Takebe, Yasuki Nakamura, N. Higaki, Haruo Kimura, H. Miyake, T. Satoh, K. Kawasaki, R. Sasagawa, W. Shibamoto, Mitsuru Sasaki, Naruyoshi Ando, Tomohiro Yamana, I. Fukushi, S. Tago, F. Hayakawa, Teruhiko Kamigata, S. Imai, Atsushi Satoh, Yasuaki Hatta, Noboru Nishimura, Y. Asada, Taizo Satoh, Takao Sukemura, S. Ando, Hiromasa Takahashi","doi":"10.1109/ISSCC.2002.992265","DOIUrl":null,"url":null,"abstract":"A 533 MHz 2.5 W 2132 MIPS 12.8 GOPS 2.1 GFLOPS 8-way VLIW embedded multimedia processor occupies a 7.8/spl times/7.8 mm/sup 2/ die in a 7-layer metal 0.11 /spl mu/m CMOS at 1.2 V. VLIW, SIMD, dynamic branch prediction, non-aligned dual load/store mechanism and a crosstalk-aware design flow contribute to performance.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"An 8-way VLIW embedded multimedia processor built in 7-layer metal 0.11 /spl mu/m CMOS technology\",\"authors\":\"H. Okano, A. Suga, T. Shiota, Y. Takebe, Yasuki Nakamura, N. Higaki, Haruo Kimura, H. Miyake, T. Satoh, K. Kawasaki, R. Sasagawa, W. Shibamoto, Mitsuru Sasaki, Naruyoshi Ando, Tomohiro Yamana, I. Fukushi, S. Tago, F. Hayakawa, Teruhiko Kamigata, S. Imai, Atsushi Satoh, Yasuaki Hatta, Noboru Nishimura, Y. Asada, Taizo Satoh, Takao Sukemura, S. Ando, Hiromasa Takahashi\",\"doi\":\"10.1109/ISSCC.2002.992265\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 533 MHz 2.5 W 2132 MIPS 12.8 GOPS 2.1 GFLOPS 8-way VLIW embedded multimedia processor occupies a 7.8/spl times/7.8 mm/sup 2/ die in a 7-layer metal 0.11 /spl mu/m CMOS at 1.2 V. VLIW, SIMD, dynamic branch prediction, non-aligned dual load/store mechanism and a crosstalk-aware design flow contribute to performance.\",\"PeriodicalId\":423674,\"journal\":{\"name\":\"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)\",\"volume\":\"3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2002.992265\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2002.992265","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 11

摘要

533 MHz 2.5 W 2132 MIPS 12.8 GOPS 2.1 GFLOPS 8路VLIW嵌入式多媒体处理器在1.2 V电压下，采用7层金属0.11 /spl mu/m CMOS芯片，占用7.8/spl次/7.8 mm/sup / 2/芯片。VLIW、SIMD、动态分支预测、非对齐双负载/存储机制和串扰感知设计流程有助于提高性能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

An 8-way VLIW embedded multimedia processor built in 7-layer metal 0.11 /spl mu/m CMOS technology

A 533 MHz 2.5 W 2132 MIPS 12.8 GOPS 2.1 GFLOPS 8-way VLIW embedded multimedia processor occupies a 7.8/spl times/7.8 mm/sup 2/ die in a 7-layer metal 0.11 /spl mu/m CMOS at 1.2 V. VLIW, SIMD, dynamic branch prediction, non-aligned dual load/store mechanism and a crosstalk-aware design flow contribute to performance.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)

自引率

0.00%

发文量