Extended use of pseudo-flash reset technique for an active pixel with logarithmic compressed response

The pseudo-flash reset (P-FRST) is a technique used to reduce image lag in CMOS active-pixel sensors (APS). The compact pixel topology consisting of a photodetector and three FETs (3T APS) is widely employed because of its large fill factor combined with the possibility to operate in both linear and logarithmic compressed-response (LCR) modes. The use of these two modes in a single readout cycle yields good low-light sensitivity and extended dynamic range (DR). However, fabrication non idealities result in fixed-pattern noise (FPN) across the image-sensor chip and cannot be reduced by classical double-sampling readout subtraction (DSRS). In the present work, we propose an extended use of the P-FRST technique to provide an adequate voltage reference on pixel, in order to enable DSRS, thus reducing FPN in conventional 3T APS operating in mixed linear-LCR mode.