Implementation of a hardware branch-predictor evaluation platform based on FPGAs

Branch prediction is an important topic in modern Computer Architecture research. Predictors attempt to improve the performance of a processor with a reasonable HW cost. In the last decade, many prediction schemes have been developed in order to achieve this objective, each of them with different cost/performance trade-offs. Identifying the optimal predictor for a given architecture and set of applications is an important issue that involves carrying out extensive simulations. Normally this exploration is carried out using SW emulation tools. However, this approach provides very slow simulation speeds, making it unfeasible for large design-space explorations. In this context, our work presents an important contribution, since we have developed a HW platform, based on FPGAs, for evaluating branch predictors. This platform allows us to evaluate in parallel representative branch prediction schemes, while executing the benchmarks in a SPARC v8 processor implemented in the FPGA. Our approach is several orders of magnitude faster than traditional SWbased approaches, and it not only provides accurate performance statistics but also reports the area cost and the maximum operating frequency of each predictor. In addition, our platform can be easily extended for other processor architectures as long as its HDL codes are available.