{"title":"SRAM单元的稳定性和软错误率","authors":"B. Chappell, S. Schuster, G. Sai-Halasz","doi":"10.1109/ISSCC.1984.1156666","DOIUrl":null,"url":null,"abstract":"Graphical techniques for analyzing the impact of device sizes, threshold tracking, load resistor values and other design parameters on the stability and soft error rate of SRAMs, illustrated via applicat)ons to a high-speed 64K RAM, will be presented.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"22 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Stability and soft error rates of SRAM cells\",\"authors\":\"B. Chappell, S. Schuster, G. Sai-Halasz\",\"doi\":\"10.1109/ISSCC.1984.1156666\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Graphical techniques for analyzing the impact of device sizes, threshold tracking, load resistor values and other design parameters on the stability and soft error rate of SRAMs, illustrated via applicat)ons to a high-speed 64K RAM, will be presented.\",\"PeriodicalId\":260117,\"journal\":{\"name\":\"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"volume\":\"22 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1984.1156666\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1984.1156666","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Graphical techniques for analyzing the impact of device sizes, threshold tracking, load resistor values and other design parameters on the stability and soft error rate of SRAMs, illustrated via applicat)ons to a high-speed 64K RAM, will be presented.
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