{"title":"基于InAs纳米线的栅极全隧穿场效应管的系统级优化与基准测试","authors":"C. Pan, A. Ceyhan, A. Naeemi","doi":"10.1109/ISQED.2013.6523610","DOIUrl":null,"url":null,"abstract":"The ON/OFF current and input capacitance of InAs nanowire based gate-all-around (GAA) tunnel FETs are modeled. Based on the device- and system-level models, optimization has been done and comparison has been made between TFETs and CMOS devices under different constraints for both single- and multi-core processors. Several performance metrics have been analyzed, which shows that optimal numbers of cores, power density and die size area exist for maximizing various design targets.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"System-level optimization and benchmarking for InAs nanowire based gate-all-around tunneling FETs\",\"authors\":\"C. Pan, A. Ceyhan, A. Naeemi\",\"doi\":\"10.1109/ISQED.2013.6523610\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The ON/OFF current and input capacitance of InAs nanowire based gate-all-around (GAA) tunnel FETs are modeled. Based on the device- and system-level models, optimization has been done and comparison has been made between TFETs and CMOS devices under different constraints for both single- and multi-core processors. Several performance metrics have been analyzed, which shows that optimal numbers of cores, power density and die size area exist for maximizing various design targets.\",\"PeriodicalId\":127115,\"journal\":{\"name\":\"International Symposium on Quality Electronic Design (ISQED)\",\"volume\":\"5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-03-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Symposium on Quality Electronic Design (ISQED)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISQED.2013.6523610\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Symposium on Quality Electronic Design (ISQED)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISQED.2013.6523610","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
System-level optimization and benchmarking for InAs nanowire based gate-all-around tunneling FETs
The ON/OFF current and input capacitance of InAs nanowire based gate-all-around (GAA) tunnel FETs are modeled. Based on the device- and system-level models, optimization has been done and comparison has been made between TFETs and CMOS devices under different constraints for both single- and multi-core processors. Several performance metrics have been analyzed, which shows that optimal numbers of cores, power density and die size area exist for maximizing various design targets.
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