{"title":"加载对CMOS锁存器亚稳参数的影响","authors":"C. Portmann, T. Meng","doi":"10.1109/VLSIC.1993.920520","DOIUrl":null,"url":null,"abstract":"We have discussed the behavior of buffered and unbuffered latches versus loading from a metastable performance viewpoint. A formula to determine T/sub 0/ for a buffered latch from an unbuffered one has been described. Measured results were presented for buffered and unbuffered latches. The results shown here are relevant to standard cell or gate array ASIC designers who generally use cells contained within a library and have little control over the cells, but some control over the selection and loading. Our results show the buffered version is superior for all fanouts greater than one; however, the MTBF performance is still exponentially related to loading.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"33 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Loading effects on metastable parameters of CMOS latches\",\"authors\":\"C. Portmann, T. Meng\",\"doi\":\"10.1109/VLSIC.1993.920520\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We have discussed the behavior of buffered and unbuffered latches versus loading from a metastable performance viewpoint. A formula to determine T/sub 0/ for a buffered latch from an unbuffered one has been described. Measured results were presented for buffered and unbuffered latches. The results shown here are relevant to standard cell or gate array ASIC designers who generally use cells contained within a library and have little control over the cells, but some control over the selection and loading. Our results show the buffered version is superior for all fanouts greater than one; however, the MTBF performance is still exponentially related to loading.\",\"PeriodicalId\":127467,\"journal\":{\"name\":\"Symposium 1993 on VLSI Circuits\",\"volume\":\"33 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-05-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Symposium 1993 on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.1993.920520\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Symposium 1993 on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1993.920520","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Loading effects on metastable parameters of CMOS latches
We have discussed the behavior of buffered and unbuffered latches versus loading from a metastable performance viewpoint. A formula to determine T/sub 0/ for a buffered latch from an unbuffered one has been described. Measured results were presented for buffered and unbuffered latches. The results shown here are relevant to standard cell or gate array ASIC designers who generally use cells contained within a library and have little control over the cells, but some control over the selection and loading. Our results show the buffered version is superior for all fanouts greater than one; however, the MTBF performance is still exponentially related to loading.
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