{"title":"一种提高PRML读通道锁相环捕获范围的技术","authors":"C. Srinivasan","doi":"10.1109/ICVD.1998.646593","DOIUrl":null,"url":null,"abstract":"A new technique to improve the capture range of a Phase Locked Loop (PLL) in the context of partial response signalling is presented. A known preamble is transmitted at the beginning to aid phase and frequency locking. Previous timing recovery techniques have a false locking problem for large initial frequency errors. The new technique eliminates this problem by using information available in the sampled preamble sequence. The improvement obtained is demonstrated using computer simulations.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"516 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A technique to improve capture range of a PLL in PRML read channel\",\"authors\":\"C. Srinivasan\",\"doi\":\"10.1109/ICVD.1998.646593\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new technique to improve the capture range of a Phase Locked Loop (PLL) in the context of partial response signalling is presented. A known preamble is transmitted at the beginning to aid phase and frequency locking. Previous timing recovery techniques have a false locking problem for large initial frequency errors. The new technique eliminates this problem by using information available in the sampled preamble sequence. The improvement obtained is demonstrated using computer simulations.\",\"PeriodicalId\":139023,\"journal\":{\"name\":\"Proceedings Eleventh International Conference on VLSI Design\",\"volume\":\"516 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1998-01-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings Eleventh International Conference on VLSI Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICVD.1998.646593\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Eleventh International Conference on VLSI Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICVD.1998.646593","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A technique to improve capture range of a PLL in PRML read channel
A new technique to improve the capture range of a Phase Locked Loop (PLL) in the context of partial response signalling is presented. A known preamble is transmitted at the beginning to aid phase and frequency locking. Previous timing recovery techniques have a false locking problem for large initial frequency errors. The new technique eliminates this problem by using information available in the sampled preamble sequence. The improvement obtained is demonstrated using computer simulations.