{"title":"一种基于dll的唤醒接收机偏置校准环路技术","authors":"Y. Xie, Xufeng Liao, Xincai Liu, Lianxi Liu","doi":"10.1109/ICTA56932.2022.9963030","DOIUrl":null,"url":null,"abstract":"A DLL-based offset calibration loop (OCL) is proposed to eliminate the DC offset and low-frequency flicker noise of the two differential paths to optimize the input signal-to-noise ratio before signal demodulation. The loop technology that can effectively calibrate the offset reduces the false alarm rate of the wake-up receiver (WuRX), and improves the sensitivity and robustness. This design uses 65nm LP CMOS process for layout design and simulation verification. With a supply voltage of 0.4V, the DC offset voltage on the signal path is reduced from an initial 5mV to a calibrated 39µV, resulting in a total system power consumption of 7.4nW.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"137 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A DLL-Based Offset Calibration Loop Technology for Wake-Up Receivers\",\"authors\":\"Y. Xie, Xufeng Liao, Xincai Liu, Lianxi Liu\",\"doi\":\"10.1109/ICTA56932.2022.9963030\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A DLL-based offset calibration loop (OCL) is proposed to eliminate the DC offset and low-frequency flicker noise of the two differential paths to optimize the input signal-to-noise ratio before signal demodulation. The loop technology that can effectively calibrate the offset reduces the false alarm rate of the wake-up receiver (WuRX), and improves the sensitivity and robustness. This design uses 65nm LP CMOS process for layout design and simulation verification. With a supply voltage of 0.4V, the DC offset voltage on the signal path is reduced from an initial 5mV to a calibrated 39µV, resulting in a total system power consumption of 7.4nW.\",\"PeriodicalId\":325602,\"journal\":{\"name\":\"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)\",\"volume\":\"137 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-10-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICTA56932.2022.9963030\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICTA56932.2022.9963030","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A DLL-Based Offset Calibration Loop Technology for Wake-Up Receivers
A DLL-based offset calibration loop (OCL) is proposed to eliminate the DC offset and low-frequency flicker noise of the two differential paths to optimize the input signal-to-noise ratio before signal demodulation. The loop technology that can effectively calibrate the offset reduces the false alarm rate of the wake-up receiver (WuRX), and improves the sensitivity and robustness. This design uses 65nm LP CMOS process for layout design and simulation verification. With a supply voltage of 0.4V, the DC offset voltage on the signal path is reduced from an initial 5mV to a calibrated 39µV, resulting in a total system power consumption of 7.4nW.