{"title":"10GBASE-T以太网接收机1Gs/s开环跟踪保持设计","authors":"M. Tonelli, A. Boni, C. Azzolini","doi":"10.1109/RME.2009.5201306","DOIUrl":null,"url":null,"abstract":"A 1Gs/s CMOS Track-and-Hold for the upcoming generation of Ethernet applications (10GBASE-T) is presented. The Track-and-Hold is designed to be employed as front-end in a time-interleaved analog-to-digital converter and it is based on an open-loop architecture composed of an input buffer and a highspeed switch. The proposed Track-and-Hold, designed in a 65nm low-power CMOS process, exhibits a total harmonic distortion lower than −80dB and a spurious free dynamic range better than 79dB, with a power consumption lower than 11mW (dual supply voltages 1.2V/2.5V, 1.85mA/4.22mA).","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Design of 1Gs/s open-loop Track-and-Hold for 10GBASE-T Ethernet receivers\",\"authors\":\"M. Tonelli, A. Boni, C. Azzolini\",\"doi\":\"10.1109/RME.2009.5201306\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 1Gs/s CMOS Track-and-Hold for the upcoming generation of Ethernet applications (10GBASE-T) is presented. The Track-and-Hold is designed to be employed as front-end in a time-interleaved analog-to-digital converter and it is based on an open-loop architecture composed of an input buffer and a highspeed switch. The proposed Track-and-Hold, designed in a 65nm low-power CMOS process, exhibits a total harmonic distortion lower than −80dB and a spurious free dynamic range better than 79dB, with a power consumption lower than 11mW (dual supply voltages 1.2V/2.5V, 1.85mA/4.22mA).\",\"PeriodicalId\":245992,\"journal\":{\"name\":\"2009 Ph.D. Research in Microelectronics and Electronics\",\"volume\":\"17 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-07-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 Ph.D. Research in Microelectronics and Electronics\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RME.2009.5201306\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 Ph.D. Research in Microelectronics and Electronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RME.2009.5201306","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of 1Gs/s open-loop Track-and-Hold for 10GBASE-T Ethernet receivers
A 1Gs/s CMOS Track-and-Hold for the upcoming generation of Ethernet applications (10GBASE-T) is presented. The Track-and-Hold is designed to be employed as front-end in a time-interleaved analog-to-digital converter and it is based on an open-loop architecture composed of an input buffer and a highspeed switch. The proposed Track-and-Hold, designed in a 65nm low-power CMOS process, exhibits a total harmonic distortion lower than −80dB and a spurious free dynamic range better than 79dB, with a power consumption lower than 11mW (dual supply voltages 1.2V/2.5V, 1.85mA/4.22mA).
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