Opto-electrical analog front-end with rapid power-on and 0.82 pJ/bit for 28 Gb/s in 14 nm FinFET CMOS

This paper presents the design and the opto-electrical measurements of a power-efficient receiver analog front-end (AFE) for optical communication with standby mode and rapid recovery time below 10 ns. The circuit was designed and fabricated in advanced 14 nm FinFET CMOS with a small area of 0.0159mm2. The AFE consumes 22.6mW power, thus achieving a power efficiency of 0.82 pJ/bit. Furthermore, a power saving standby mode is supported which is a feature not commonly available in state-of-the-art designs. During the powersaving mode, the limiting amplifier (LA) is shut down resulting in power consumption reduction of 50 % down to 11.4 mW. A recovery time from standby mode amounting to 8.2 ns was measured, thus making the front-end suitable for future standard burst mode operation. For measurements, a multi-chip assembly with a photo diode in 850 nm band was fabricated and the performance was measured using an optical probe. A bit error rate (BER) of 10−12 was achieved for a data rate of 28 Gb/s with an optical sensitivity of −3.5 dBm optical modulation amplitude (OMA).