Y. Tanaka, H. Takatani, H. Fujita, Y. Oizono, Y. Nabeshima, T. Sudo, A. Sakai, S. Uchiyama, H. Ikeda
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引用次数: 3
摘要
研究了具有4k-IO宽总线结构的3D系统封装(SiP)的同步交换输出缓冲器(SSO)噪声和配电网络(PDN)阻抗。3D SiP由3个堆叠芯片和一个有机中间体组成。这三块芯片是上面的存储芯片，中间的硅中间层，下面的逻辑芯片。每个芯片的尺寸相同，都是9.93 mm × 9.93 mm。在硅中间体上形成了4096个硅通孔(TSV)。然后，将这3个堆叠芯片组装在26mm × 26mm的有机中间层上。单点登录噪声是4k-IO宽总线结构的3D SiP的关键问题之一。为此，在评估板上对微型供电系统的单点同步噪声进行了测量。采用直接接触法测量各芯片的PDN阻抗。然后合成PDN总阻抗，确定其抗谐振峰值。
Measurement of SSO noise and PDN impedance of 3D SiP with 4k-IO widebus structure
Simultaneous switching output buffer (SSO) noise and impedance of power distribution network (PDN) for a 3D systemin package (SiP) with 4k-IO widebus structure has been investigated. The 3D SiP consisted of 3 stacked chips and an organic interposer. These three chips were a memory chip on the top, a silicon interposer in the middle, and a logic chip on the bottom. The size of each chip was the same, and 9.93 mm by 9.93 mm. More than 4096 of through silicon vias (TSV's) were formed to the silicon interposer. Next, these 3 stacked chips were assembled on the organic interposer, whose size was 26 mm by 26mm. SSO noise is one of critical issues for the 3D SiP with 4k-IO widebus structure. So, the SSO noise was measured in the miniIO power supply system in an evaluation board. Furthermore the PDN impedance for each chip was measured by direct contact method. Then, the total PDN impedance was synthesized to confirm the anti-resonance peak of it.
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