{"title":"优化的超大规模集成电路设计，增强图像降阶","authors":"Honam Lee, Bonggeun Lee, Youngho Lee, B. Kang","doi":"10.1109/APASIC.2000.896928","DOIUrl":null,"url":null,"abstract":"Proposes the optimized hardware architecture for a high performance image downscaler. The proposed downscaler uses nonlinear digital filters for horizontal and vertical scalings. In order to achieve the optimization the filters are implemented with multiplexer-adder type scheme and all the filter coefficients are selected on the order of two's power. The usefulness of the scaler is also verified by comparing with a pixel drop downscaler. The proposed scaler is designed by using VHDL and implemented by using the IDEC-C632 0.65 /spl mu/m cell library.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Optimized VLSI design for enhanced image downscaler\",\"authors\":\"Honam Lee, Bonggeun Lee, Youngho Lee, B. Kang\",\"doi\":\"10.1109/APASIC.2000.896928\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Proposes the optimized hardware architecture for a high performance image downscaler. The proposed downscaler uses nonlinear digital filters for horizontal and vertical scalings. In order to achieve the optimization the filters are implemented with multiplexer-adder type scheme and all the filter coefficients are selected on the order of two's power. The usefulness of the scaler is also verified by comparing with a pixel drop downscaler. The proposed scaler is designed by using VHDL and implemented by using the IDEC-C632 0.65 /spl mu/m cell library.\",\"PeriodicalId\":313978,\"journal\":{\"name\":\"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)\",\"volume\":\"20 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-08-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APASIC.2000.896928\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APASIC.2000.896928","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Optimized VLSI design for enhanced image downscaler
Proposes the optimized hardware architecture for a high performance image downscaler. The proposed downscaler uses nonlinear digital filters for horizontal and vertical scalings. In order to achieve the optimization the filters are implemented with multiplexer-adder type scheme and all the filter coefficients are selected on the order of two's power. The usefulness of the scaler is also verified by comparing with a pixel drop downscaler. The proposed scaler is designed by using VHDL and implemented by using the IDEC-C632 0.65 /spl mu/m cell library.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
