Modeling differential Through-Silicon-Vias (TSVs) with large signal, non-linear capacitance

Through Silicon Vias (TSVs) have been mostly modeled assuming that the TSV metal-insulator-semiconductor (MIS) interface is not biased and silicon substrate is just a lossy, low conductive medium. These modeling methods are based on small signal analysis and don't consider semiconductor carrier accumulation or depletion due to static biasing or large signals. This paper argues that the complementary nature of differential signals introduces a virtual ground and that the voltage difference between a TSV and the virtual ground automatically biases TSV MIS interface, causing carrier accumulation or depletion. In the meantime, large digital signal swing makes the depletion region to change its width dynamically, which introduces a non-linear, large signal TSV capacitance. This capacitance is modeled analytically in this paper, a new equivalent circuit model for differential TSVs are proposed, and the impact on the performance of high-speed differential signals is examined in channel simulations.