0.6 V suppy voltage 0.25 /spl mu/m E/D-HJFET(IS/sup 3/T) LSI technology for low power consumption and high speed LSIs

A new technology for fabricating 0.25 /spl mu/m gate E/D-heterojunction FET LSIs is developed as a step towards the development of ultralow supply voltage LSIs. This technology, which is based upon all dry-process techniques, includes the formation of a 0.25 /spl mu/m gate opening through the use of optical lithography and inner SiO/sub 2/ sidewalls. The f/sub max/ and the g/sub max/ for a Y-shaped gate E-HJFET are 108 GHz and 530 mS/mm, respectively. Excellent performances are obtained with DCFL ring oscillators using n-AlGaAs/i-InGaAs pseudomorphic E/D-HJFETs. These include 18 ps/G unloaded delay and 109 ps/G loaded delay (FI=FO=3, L=1 mm) with 0.15 mW/G at a low supply voltage of 0.6 V, where inverters have a sufficient noise margin of more than 180 mV. Also, 10 Gbps error-free operation of a selector switch is demonstrated with 9.4 mW at 0.6 V.<>